In the manufacture of integrated circuits, and the like, it is often necessary to etch portions of a silicon wafer, for example, through the windows of an overlaying, patterned mask manufactured from some suitable resist material. Alternatively, it may be necessary to etch a thick layer of polysilicon and to terminate the etch when an underlaying thin layer of SiO.sub.2 is reached. This latter technique requires an etch process that will selectively etch polysilicon but which is inert to SiO.sub.2.
In both of the above cases, it is customary to employ a wet chemical etch; however, considerable interest has been expressed recently in the use of reactive gas plasmas to perform the etching. The reason for this is that reactive gas plasmas have been found to be anisotropic under some circumstances and, in general, are cleaner, more efficient and far less troublesome to use than wet chemical etches.
A plasma etch is typically carried out in an evacuated reaction chamber, for example, the reaction chamber disclosed by Reinberg in U.S. Pat. No. 3,757,733, which issued Sept. 11, 1973, which patent is hereby incorporated by reference as if more fully set forth herein.
As might be expected, the potential of the wafer surface, with respect to the plasma, has been found to play an important role in an RF plasma etching process. Unfortunately, heretofore, no satisfactory way has been found to establish this potential independently of the other operating parameters in the reaction chamber. Furthermore, the self-bias that is induced on the surface of the wafer by the plasma itself has been found to be very sensitive to almost all of the parameters of the etching process, including the system geometry. As a result of the above, prior art plasma etching processes have been plagued with irreproducibility and unpredictability, resulting in very low yield. Some attempts to correct this problem have been made, for example, by placing a DC bias on the electrode that carries the wafer, or by grounding the electrode through either a resistive or a capacitive impedance. Unfortunately, such attempts have not been successful for the simple reason that the potential of the electrode is not necessarily the same as the potential of the surface of a wafer supported by the electrode. This is especially true if the wafer to be etched includes a dielectric, interlevel layer, for example, a thin film of SiO.sub.2.